个人简介

蔡烁，男，博士，教授，博士生导师，湖南省普通高校青年骨干教师。中国计算机学会高级会员，中国计算机学会容错计算专委会执行委员，湖南省计算机学会理事。2004年于浙江大学信息工程专业获工学学士学位，2007年于湖南大学信号与信息处理专业获工学硕士学位，2015年于湖南大学计算机科学与技术专业获工学博士学位。从事宇航级集成电路抗辐射加固、电路系统可靠性评估、近似计算与人工智能等领域的研究。主持国家自然科学基金面上项目、青年基金项目、湖南省杰出青年基金项目等，在IEEE TVLSI、IEEE TCASⅡ、IEEE TNSE、Integration、JETTA、计算机学报、电子学报、电子与信息学报、ATS、ITC-Asia、CCF-DAC等国内外重要学术期刊和会议上发表论文40余篇。

招生方向：电子科学与技术博士和硕士（电路与系统方向），电子信息专业硕士。

主要研究领域

集成电路抗辐射加固设计、容错计算、近似计算、人工智能、电路系统可靠性。

教学情况

主讲《电路分析基础》、《模拟电子电路》、《数字电路与逻辑设计》等课程。

科研项目

[1]主持国家自然科学基金面上项目：基于相关性分离的逻辑电路失效率高效分析与敏感目标精准定位，2022-2025；

[2]主持国家自然科学基金青年基金项目：逻辑级破解纳米集成电路软错误可靠性评估难题的新方法，2018-2020；

[3]主持湖南省自然科学基金杰出青年基金项目：空间辐射环境下纳米集成电路可靠性评估与加固设计，2022-2024；

[4]主持湖南省自然科学基金面上项目：面向逻辑级超大规模集成电路软错误率分析方法研究，2020-2022；

[5]主持湖南省教育厅重点项目：空间辐射环境下纳米集成电路瞬态故障分析与可靠性评估，2019-2021；

[6]主持湖南省水利科技项目：大坝病害快速诊断与动态风险控制决策研究，2020-2022。

代表性论文

[1]Shuo Cai*, Xinjie Liang, Zhu Huang, Weizheng Wang, Fei Yu. Low Power and High Speed SRAM Cells with Double-Node Upset Self-Recovery for Reliable Applications. IEEE Transactions on Very Large Scale Integration Systems. 2025, 33(2): 475-487

[2]Shuo Cai, Huixin Gao, Jie Zhang, Ming Peng*. A self-attention-LSTM method for dam deformation prediction based on CEEMDAN optimization[J]. Applied Soft Computing. 2024(7): 111615

[3]Shuo Cai*, Xinjie Liang, Yan Wen, Fei Yu, Lairong Yin. A radiation-hardened 20T SRAM Cell with high reliability and low power consumption. 2024 IEEE International Test Conference in Asia (ITC-Asia). Changsha, China, 2024, 8. 18-20: 1-6

[4]蔡烁*, 何辉煌, 余飞, 尹来容, 刘洋. 基于相关性分离的逻辑电路敏感门定位算法. 电子与信息学报. 2024, 46(1): 362-372

[5]Shuo Cai*, Yan Wen, Caicai Xie, Weizheng Wang, Fei Yu. Low-power and high-speed SRAM Cells for Double-Node-Upset Recovery. Integration, the VLSI Journal. 2023, 91:1-9

[6]Shuo Cai*, Yan Wen, Jiangbiao Ouyang, Weizheng Wang, Fei Yu, Bo Li. A Highly Reliable and Low-Power Cross-Coupled 18T SRAM Cell. Microelectronics Journal. 2023, 134:105729:1-7

[7]Shuo Cai, Tingyu Luo, Fei Yu*, Pradip Kumar Sharma, Weizheng Wang, Lairong Yin. Reliability Analysis of Correlated Competitive and Dependent Components Considering Random Isolation Times. CMC: Computer, Materials & Continua. 2023, 76(3): 2763-2777

[8]Shuo Cai*, Jiangbiao Ouyang, Yan Wen, Weizheng Wang, Fei Yu. A Low-Delay Quadruple-Node-Upset Self-Recoverable Latch Design. 2023 IEEE 32nd Asian Test Symposium(ATS), Beijing, China, 2023,10.14-17: 1-5

[9]Shuo Cai*, Caicai Xie, Yan Wen, Weizheng Wang, Fei Yu, Lairong Yin. Four-input-C-element-based Multiple-Node-Upset-Self-Recoverable Latch Designs. Integration, the VLSI Journal. 2023, 90:11-21

[10]Shuo Cai*, Binyong He, Sicheng Wu, Jin Wang, Weizheng Wang, Fei Yu. An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation. Journal of Electronic Testing-Theory and Applications. 2022, 38(2): 165-180

[11]Shuo Cai*, Sicheng Wu, Weizheng Wang, Fei Yu, Lairong Yin. Sensitive Vector Search for Logic Circuit Failure Probability based on Improved Adaptive Cuckoo Algorithm. Journal of Semiconductor Technology and Science. 2022, 22(2): 69-83

[12]Fei Yu, Xinxin Kong, Huifeng Chen, Qiulin Yu, Shuo Cai*, Yuanyuan Huang, Sichun Du. A 6D Fractional-Order Memristive Hopfield Neural Network and its Application in Image Encryption. Frontiers in Physics. 2022, 10: 847385, 1-14

[13]Fei Yu, Huifeng Chen, Xinxin Kong, Qiulin Yu, Shuo Cai*, Yuanyuan Huang, Sichun Du. Dynamic Analysis and Application in Medical Digital Image Watermarking of a New Multi-scroll Neural Network with Quartic Nonlinear Memristor. European Physical Journal Plus. 2022, 137(4): 434

[14]Shuo Cai*, Caicai Xie, Yan Wen, Weizheng Wang. A Low-Cost Quadruple-Node-Upset Self-Recoverable Latch Design. 5th IEEE International Test Conference in Asia, ITC-Asia 2021. Shanghai,China,2021

[15]Shuo Cai*, Binyong He, Weizheng Wang, et al. Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults. Journal of Electronic Testing-Theory and Applications. 2020, 36(4): 469-483

[16]Shuo Cai*, Binyong He, Sicheng Wu, et al. An Accurate and Efficient Approach for Estimating the Failure Probability of Logic Circuits, 2020 CCF Integrated Circuit Design and Automation Conference, 2020: 1-15

[17]Shuo Cai*, Weizheng Wang, Fei Yu, Binyong He. Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits. Journal of Electronic Testing - Theory and Applications. 2019, 35(2): 163-172

[18]蔡烁*,邝继顺,张亮,刘铁桥,王伟征.基于差错传播概率矩阵的时序电路软错误可靠性评估.计算机学报. 2015, 38(5): 923-931

[19]蔡烁*,邝继顺,刘铁桥,凌纯清,尤志强.基于伯努利分布的逻辑电路可靠度计算方法.电子学报. 2015, 43(11)：2292-2297

[20]蔡烁*,邝继顺,刘铁桥,王伟征.考虑信号相关性的逻辑电路可靠度计算方法.电子学报.2014, 42(8): 1660-1664

联系方式

E-mail: caishuo@csust.edu.cn